Counters Questions and Answers

Q: The tpd for each flip-flop is 50ns, determine the maximum operating frequency for MOD-32 ripple counter :

The maximum operating frequency is 4 MHz.A MOD-32 counter needs 5 flip-flops, since \(2^5 = 32\). In a ripple counter each flip-flop is clocked by the one before it, so in the worst case the delays add up before the count settles:\[ \begin{aligned} t_{total} &= 5 \times 50\ \text{ns} = 250\ \text{ns} \\ f_{max} &= \frac{1}{250\ \text{ns}} = 4\ \text{MHz} \end{aligned} \]4 GHz is the same digits with the wrong prefix. 3 MHz and 2 MHz match no sensible count of flip-flops: 2 MHz would need ten flip-flops' delay, which is a MOD-1024 counter.

Q: Output frequency in the following diagram will be :A 1,31,072 Hz crystal drives a crystal oscillator, whose output feeds a 14-stage binary divider giving the output fo.

The output frequency is 8 Hz.Each stage of a binary divider (one flip-flop) halves the frequency, so 14 stages divide by \(2^{14}\):\[ \begin{aligned} 2^{14} &= 16384 \\ f_{o} &= \frac{131072}{16384} = 8\ \text{Hz} \end{aligned} \]131072 is \(2^{17}\), so the result is \(2^{3}\) exactly. 1 kHz or 100 Hz would need a decimal (divide-by-10) chain, and 13 Hz does not come from dividing by any power of two.

Q: A 4-bit ring counter is loaded with 1000 data and 100 kHz clock input. The output at \(Q_0\) would be :

The output at \(Q_0\) is 25 kHz with 25% duty cycle.A 4-bit ring counter loaded with 1000 circulates the single 1 through its four stages, so each output is high for one clock period out of every four. The output frequency and duty cycle are\[ \begin{aligned} f &= \frac{100\ \text{kHz}}{4} = 25\ \text{kHz} \\ D &= \frac{1}{4} = 25\% \end{aligned} \]50 kHz would come from dividing by 2, as a single toggle flip-flop does, and a 50% duty cycle would need the output high for two of the four clock periods, as in a Johnson counter.

Q: A four-bit ripple counter consists of flip-flops that each have a propagation delay from clock to Q output of 12 ns. For the counter of recycle from 1111 to 0000; it will take a total delay of :

The total delay is 48 ns.In a ripple (asynchronous) counter, each flip-flop is clocked by the output of the one before it. Going from 1111 to 0000, every bit toggles, and each toggle waits for the previous one, so the delays add:\[ t = 4 \times 12\ \text{ns} = 48\ \text{ns} \]12 ns would be the delay of a synchronous counter, where all flip-flops are clocked together. 24 and 36 ns count only two or three of the four stages.

Q: Modulo 6 counter can be built with .............. flip flops.

A modulo-6 counter needs 3 flip-flops.n flip-flops give up to \(2^{n}\) states, so the smallest n with \(2^{n} \ge 6\) is needed: \(2^{2} = 4\) is too few and \(2^{3} = 8\) is enough. A 3-bit counter is made to reset after state 5 (101), giving the six states 0 to 5.Two flip-flops give only four states. Four flip-flops would work but are more than needed. Six flip-flops would be used only in a ring counter, which needs one flip-flop per state, not in a binary modulo counter.

11.

The t_pd for each flip-flop is 50ns, determine the maximum operating frequency for MOD-32 ripple counter :

A.4 MHz
B.3 MHz
C.4 GHz
D.2 MHz

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: A

The maximum operating frequency is 4 MHz.

A MOD-32 counter needs 5 flip-flops, since \(2^5 = 32\). In a ripple counter each flip-flop is clocked by the one before it, so in the worst case the delays add up before the count settles:

\[ \begin{aligned} t_{total} &= 5 \times 50\ \text{ns} = 250\ \text{ns} \\ f_{max} &= \frac{1}{250\ \text{ns}} = 4\ \text{MHz} \end{aligned} \]

4 GHz is the same digits with the wrong prefix. 3 MHz and 2 MHz match no sensible count of flip-flops: 2 MHz would need ten flip-flops' delay, which is a MOD-1024 counter.

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12.

Output frequency in the following diagram will be :

A 1,31,072 Hz crystal drives a crystal oscillator, whose output feeds a 14-stage binary divider giving the output f_o.

A.1 kHz
B.100 Hz
C.13 Hz
D.8 Hz

Exam Year(s)

MH SET - 2021, SET Exam - 2021,

Answer: D

The output frequency is 8 Hz.

Each stage of a binary divider (one flip-flop) halves the frequency, so 14 stages divide by \(2^{14}\):

\[ \begin{aligned} 2^{14} &= 16384 \\ f_{o} &= \frac{131072}{16384} = 8\ \text{Hz} \end{aligned} \]

131072 is \(2^{17}\), so the result is \(2^{3}\) exactly. 1 kHz or 100 Hz would need a decimal (divide-by-10) chain, and 13 Hz does not come from dividing by any power of two.

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13.

A 4-bit ring counter is loaded with 1000 data and 100 kHz clock input. The output at \(Q_0\) would be :

A.50 kHz with 50% duty cycle
B.25 kHz with 25% duty cycle
C.50 kHz with 25% duty cycle
D.25 kHz with 50% duty cycle

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: B

The output at \(Q_0\) is 25 kHz with 25% duty cycle.

A 4-bit ring counter loaded with 1000 circulates the single 1 through its four stages, so each output is high for one clock period out of every four. The output frequency and duty cycle are

\[ \begin{aligned} f &= \frac{100\ \text{kHz}}{4} = 25\ \text{kHz} \\ D &= \frac{1}{4} = 25\% \end{aligned} \]

50 kHz would come from dividing by 2, as a single toggle flip-flop does, and a 50% duty cycle would need the output high for two of the four clock periods, as in a Johnson counter.

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14.

The expression for number of modulo of a ripple counter with 'n' flip-flop is :

A.\(2^{n}\)
B.\(n\)
C.\(2^{n} - 1\)
D.\(n^{2}\)

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: A

A ripple counter with \(n\) flip-flops has a maximum modulus of \(2^{n}\).

Each flip-flop stores one bit, so \(n\) flip-flops hold \(n\) bits and can represent \(2^{n}\) distinct states. A straight binary ripple counter steps through all of them, 0 to \(2^{n} - 1\), before returning to 0, so it divides the clock by \(2^{n}\). For example, a 4-bit ripple counter counts 0 to 15 and is a mod-16 counter.

\(2^{n} - 1\) is the largest count reached, not the number of states, which is the common slip. \(n\) is the number of states of a ring counter with \(n\) flip-flops, and \(n^{2}\) has no meaning here.

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15.

A four-bit ripple counter consists of flip-flops that each have a propagation delay from clock to Q output of 12 ns. For the counter of recycle from 1111 to 0000; it will take a total delay of :

A.12 ns
B.24 ns
C.36 ns
D.48 ns

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: D

The total delay is 48 ns.

In a ripple (asynchronous) counter, each flip-flop is clocked by the output of the one before it. Going from 1111 to 0000, every bit toggles, and each toggle waits for the previous one, so the delays add:

\[ t = 4 \times 12\ \text{ns} = 48\ \text{ns} \]

12 ns would be the delay of a synchronous counter, where all flip-flops are clocked together. 24 and 36 ns count only two or three of the four stages.

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16.

In a 4-bit ripple counter, how many clock pulse are required for a complete counting cycle ?

A.4
B.8
C.16
D.2

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: C

A 4-bit ripple counter needs 16 clock pulses for a complete cycle.

An n-bit binary counter has \(2^{n}\) states. For n = 4 it counts 0000 to 1111, 0 to 15, which is 16 states, so 16 clock pulses take it through every state and back to 0000. Its modulus is 16.

4 is the number of flip-flops, not the number of states. 8 is the number of states of a 3-bit counter, and 2 that of a single flip-flop.

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17.

Modulo 6 counter can be built with .............. flip flops.

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: B

A modulo-6 counter needs 3 flip-flops.

n flip-flops give up to \(2^{n}\) states, so the smallest n with \(2^{n} \ge 6\) is needed: \(2^{2} = 4\) is too few and \(2^{3} = 8\) is enough. A 3-bit counter is made to reset after state 5 (101), giving the six states 0 to 5.

Two flip-flops give only four states. Four flip-flops would work but are more than needed. Six flip-flops would be used only in a ring counter, which needs one flip-flop per state, not in a binary modulo counter.

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