CMOS Fabrication Process Questions and Answers

Q: One can get information on chemical composition of samples using :

Chemical composition is obtained with EDAX.In energy-dispersive X-ray analysis, the electron beam of an electron microscope knocks inner-shell electrons out of the atoms in the sample. As the atoms relax they emit X-rays whose energies are characteristic of each element, so the spectrum shows which elements are present and in what proportion.TEM gives images and diffraction patterns of the internal structure, SEM alone images surface topography, and XRD gives crystal structure and phase. None of them on its own measures elemental composition.

Q: Which of the following statements is true in case of CMOS fabrication?

The key gives Fabrication of p-MOS transistor requires few additional steps compared to n-MOS transistor.In the common n-well CMOS process the starting wafer is p-type, so the nMOS transistors are built directly in the substrate. The pMOS transistors need an n-type region to sit in, which means extra steps: an n-well mask, the n-well implant and drive-in, and a separate p+ source/drain implant with its own mask. So the pMOS device is the one that costs additional processing.The first option reverses this. The second is wrong because the two devices need different well and implant steps, and the third, while loosely true, does not identify the specific point the question tests.

Q: As die size shrinks. the complexity of making the photomasks ...........

As die size shrinks, the complexity of making photomasks increases.Shrinking a die means shrinking its features. Smaller lines and spaces have to be written on the mask with tighter dimensional tolerance and tighter alignment between layers, and once features fall below the wavelength of the exposure light, the mask also needs optical proximity correction, phase-shift features and sub-resolution assist features to print correctly. Each step adds to mask writing time, inspection and cost.The complexity therefore cannot decrease or stay the same, and the trend is well established, so it is not something that 'cannot be determined'.

Q: Where are the silicon wafers placed in the reaction chamber for the epitaxial growth process ?

The key gives Boats.In furnace-type processing the wafers are stood or laid in a carrier called a boat (quartz, or graphite coated with silicon carbide in an epitaxial reactor, where the heated carrier is also called the susceptor) and pushed into the reaction chamber. The gas carrying the silicon source, for example silicon tetrachloride or silane in hydrogen, flows over the heated wafers and deposits a single-crystal silicon layer.An ingot is the large single crystal grown by the Czochralski process, from which wafers are sliced, so wafers are not placed in it. A crucible holds molten silicon during crystal growth, not wafers. 'Cup' is not the term used for a wafer carrier.

Q: The chemical used for shielding the active areas to achieve selective oxide growth is :

The masking chemical is silicon nitride.In the LOCOS (local oxidation of silicon) process, a patterned layer of silicon nitride, Si3N4, covers the active areas where transistors will be built. Oxygen and water vapour diffuse through nitride extremely slowly, so the field oxide grows only in the exposed regions, isolating neighbouring devices.Silver nitride is not used in silicon processing. Hydrofluoric acid etches silicon dioxide; it removes oxide rather than masking against its growth. Polysilicon is used for gates and as a buffer layer in some LOCOS variants, but it oxidises readily and is not the mask itself.

Q: Which of the following is used to obtain silicon single crystal structure while fabricating integrating circuits ?

Single-crystal silicon layers are obtained by epitaxial growth.Epitaxy deposits a thin layer of silicon on a single-crystal wafer so that the new layer continues the crystal structure of the substrate. It is used, for example, to grow a lightly doped layer over a heavily doped substrate or buried layer, as in bipolar ICs, with doping controlled independently of the substrate.Oxidation grows amorphous silicon dioxide, not crystal silicon. Photolithography transfers patterns. Wafer preparation produces the starting substrate; it does not build up single-crystal layers during IC fabrication, which is what the question asks.

21.

One can get information on chemical composition of samples using :

A.EDAX
B.TEM
C.SEM only
D.XRD

Exam Year(s)

MH SET - 2023, SET Exam - 2023,

Answer: A

Chemical composition is obtained with EDAX.

In energy-dispersive X-ray analysis, the electron beam of an electron microscope knocks inner-shell electrons out of the atoms in the sample. As the atoms relax they emit X-rays whose energies are characteristic of each element, so the spectrum shows which elements are present and in what proportion.

TEM gives images and diffraction patterns of the internal structure, SEM alone images surface topography, and XRD gives crystal structure and phase. None of them on its own measures elemental composition.

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22.

Which of the following statements is true in case of CMOS fabrication?

A.Fabrication of n-mos transistor requires few additional steps compared to p-MOS transistor
B.Fabrication on n-MOS is same as that of p-MOS transistor
C.Fabrication on n-MOS is different from that of p-MOS transistor
D.Fabrication of p-MOS transistor requires few additional steps compared to n-MOS transistor

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: D

The key gives Fabrication of p-MOS transistor requires few additional steps compared to n-MOS transistor.

In the common n-well CMOS process the starting wafer is p-type, so the nMOS transistors are built directly in the substrate. The pMOS transistors need an n-type region to sit in, which means extra steps: an n-well mask, the n-well implant and drive-in, and a separate p+ source/drain implant with its own mask. So the pMOS device is the one that costs additional processing.

The first option reverses this. The second is wrong because the two devices need different well and implant steps, and the third, while loosely true, does not identify the specific point the question tests.

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23.

As die size shrinks. the complexity of making the photomasks ...........

A.increases
B.decreases
C.remains the same
D.cannot be determined

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: A

As die size shrinks, the complexity of making photomasks increases.

Shrinking a die means shrinking its features. Smaller lines and spaces have to be written on the mask with tighter dimensional tolerance and tighter alignment between layers, and once features fall below the wavelength of the exposure light, the mask also needs optical proximity correction, phase-shift features and sub-resolution assist features to print correctly. Each step adds to mask writing time, inspection and cost.

The complexity therefore cannot decrease or stay the same, and the trend is well established, so it is not something that 'cannot be determined'.

Discuss in Forum

24.

Where are the silicon wafers placed in the reaction chamber for the epitaxial growth process ?

A.Cup
B.Boats
C.Ingots
D.Crucible

Exam Year(s)

MH SET - 2024, SET Exam - 2024,

Answer: B

The key gives Boats.

In furnace-type processing the wafers are stood or laid in a carrier called a boat (quartz, or graphite coated with silicon carbide in an epitaxial reactor, where the heated carrier is also called the susceptor) and pushed into the reaction chamber. The gas carrying the silicon source, for example silicon tetrachloride or silane in hydrogen, flows over the heated wafers and deposits a single-crystal silicon layer.

An ingot is the large single crystal grown by the Czochralski process, from which wafers are sliced, so wafers are not placed in it. A crucible holds molten silicon during crystal growth, not wafers. 'Cup' is not the term used for a wafer carrier.

Discuss in Forum

25.

The chemical used for shielding the active areas to achieve selective oxide growth is :

A.Silver Nitride
B.Silicon Nitride
C.Hydrofluoric acid
D.Polysilicon

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: B

The masking chemical is silicon nitride.

In the LOCOS (local oxidation of silicon) process, a patterned layer of silicon nitride, Si₃N₄, covers the active areas where transistors will be built. Oxygen and water vapour diffuse through nitride extremely slowly, so the field oxide grows only in the exposed regions, isolating neighbouring devices.

Silver nitride is not used in silicon processing. Hydrofluoric acid etches silicon dioxide; it removes oxide rather than masking against its growth. Polysilicon is used for gates and as a buffer layer in some LOCOS variants, but it oxidises readily and is not the mask itself.

Discuss in Forum

26.

Which of the following is used to obtain silicon single crystal structure while fabricating integrating circuits ?

A.Oxidation
B.Epitaxial growth
C.Photolithography
D.Silicon wafer preparations

Exam Year(s)

MH SET - 2025, SET Exam - 2025,

Answer: B

Single-crystal silicon layers are obtained by epitaxial growth.

Epitaxy deposits a thin layer of silicon on a single-crystal wafer so that the new layer continues the crystal structure of the substrate. It is used, for example, to grow a lightly doped layer over a heavily doped substrate or buried layer, as in bipolar ICs, with doping controlled independently of the substrate.

Oxidation grows amorphous silicon dioxide, not crystal silicon. Photolithography transfers patterns. Wafer preparation produces the starting substrate; it does not build up single-crystal layers during IC fabrication, which is what the question asks.

Discuss in Forum

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